Isolation trenches are employed in the field of integrated circuits to provide electrical insulation between devices realized, for instance, on a single chip. For example, in the field of silicon on insulator technology (SOI), isolation trenches as deep as the silicon layer are employed in order to define active silicon regions of the device that are effectively insulated from each other.
In particular, when the isolation trenches are so deep so as to contact the insulator layer of the SOI device, the silicon layer is divided into volumes of semiconductor material which are insulated from each other. Each of these volumes defines an active region of the device inside which a plurality of electrical components can be engineered. The presence of isolation trenches helps the achievement of high breakdown voltages, for instance of the order of 100 Volts or more.
The structural and morphological properties of the isolation trenches are important for effective insulation and for avoiding electrical problems such as parasitic capacitances, especially in high voltage devices. In particular, the presence of defects such as impurities, holes, or cracks in an isolation trench can strongly deteriorate the isolation properties of the trench.
The properties of the isolation trenches and, in particular, the number and the nature of the defects in the structure of the trench strongly depend on the process employed for the fabrication of the trench.
Examples of fabrication processes employed for the realization of isolation trenches in a semiconductor layer known in the art are schematically shown in FIGS 1a-1c. The figures schematically display the fabrication of two isolation trenches 110 and 120 in a SOI system. The system comprises a substrate 101, an insulator layer 102 and a silicon layer divided into active regions 103A, 103B and 103C. Moreover, the system is provided with the isolation trenches 110 and 120. The depth of the isolation trenches 110 and 120 correspond to the thickness of the silicon layer so that the trenches 110 and 120 are in contact with the insulation layer 102. In particular, the isolation trench 110 separates the active region 103A of the semiconductor layer from the active region 103B. The isolation trench 120 separates the active region 103B from the active region 103C. The active region 103B is further provided with field oxide regions 131, 132 and 133. The field oxide regions 131, 132 and 133 provide the local insulation for the components engineered in the active region 103B.
The fabrication of the trenches 110 and 120 up to the stage shown in FIG. 1a is typically performed by photolithography, oxidation and deposition techniques. In particular, after realizing the hard mask with a nitride layer 140 on the upper surface of the device, the lateral dimensions and the positions of the trenches are fixed by photolithography. In particular, a resist layer is deposited on the system and it is patterned so as to define the positions and the dimensions of the trenches. Dry etching processes are performed so as to remove the portions of the hard mask in correspondence to the positions of the trenches to be realized. Subsequently, the resist is removed and the semiconductor layer is etched so as to dig the cavities which will house the trenches. In order to fill the cavities with insulating material, a thermal oxidation process is performed so as to cover the side walls of the cavity by a liner oxide. Finally, the cavities are filled by a deposited-oxide. In particular, the cavities are filled by TEOS oxide. This is typically achieved by thermal TEOS-CVD processes wherein Tetraethyl Orthosilicate (TEOS) is employed as a source for silicon dioxide (SiO2) which fills the trenches. In particular, the decomposition of TEOS at elevated temperatures (˜700° C.) allows the growth of SiO2 films on the liner oxide formed by thermal oxidation of the side walls of the cavity.
TEOS oxide grows accordingly in the cavity with two growing fronts facing one another and developing from the side walls. Once the two fronts meet, the cavity is filled by insulating material and the process is stopped. The interface formed by the two facing growing fronts of TEOS oxide is a critical region of the trench and it is the source of several structural and morphological problems as described in detail below.
Since TEOS oxide exhibits worse structural and morphological properties than thermal oxide, in particular since the mechanical hardness of TEOS oxide is lower than the mechanical hardness of thermal oxide, the system is annealed in order to increase the hardness of the TEOS oxide.
Finally, chemical mechanical polishing (CMP) is performed in order to remove the excess oxide. In particular, CMP is employed in order to adjust the height of the trench to the height of the other components. As shown in FIG. 1a, the nitride layer 140 is used as stopping layer to achieve the end point of the CMP process.
The oxides left after CMP, especially on the active areas of the device, are typically removed. This is performed by etching processes in the presence of a mask protecting the trenches. In particular, as shown in FIG. 1b, a protection mask comprising the elements 112 and 122 in correspondence with the trenches 110 and 120, respectively, is deposited on the system. Finally, the nitride layer 140 and the residual sacrificial nitrides are removed by wet-etching processes.
These etching processes and, in particular, the etching processes performed by hydrofluoric acid (HF) may damage the isolation trenches and strongly affect their insulation properties. Openings and cracks formed in the trenches as a consequence of the etching processes worsen the structural properties of the trenches and, ultimately, their insulation properties.
One of the most critical regions in this respect is the interface formed in the trench between the TEOS growing fronts. This interface can be easily damaged and re-opened down to several depths. In the worst cases, the interface formed between the TEOS growing fronts can be even opened along the entire depth of the trench creating a sort of deep well.
The openings and cracks formed in the TEOS oxide of the trench and, in particular, the deep well formed at the interface between the growing fronts can contain several kinds of materials which are subsequently deposited on the system. As an example, further deposition of polysilicon, for instance for the purpose of forming electronic components on the active areas of the device, results in the accumulation of this material also in the openings formed in the isolation trenches.
The presence of these electrically floating volumes of polysilicon in the isolation trenches may be harmful for the insulation properties of the trenches.
In general, devices provided with isolation trenches having openings, cracks or areas filled with polysilicon or with other kinds of materials may be unreliable, especially for applications involving high voltages.
Given these drawbacks with the existing technology, it would be advantageous to provide a method which allows the fabrication of reliable isolation trenches. Moreover, it would be advantageous to provide semiconductor devices with isolation trenches having more desirable isolation properties.